1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and particularly to a semiconductor device manufacturing method involving conducting wafer aging in the course of manufacture of the semiconductor device, then making probe inspection, and feeding back the results of the inspection to a wafer fabrication process.
2. Description of the Prior Art
The conventional semiconductor device manufacturing process will now be described with reference to FIG. 8. The semiconductor device manufacturing process is broadly divided into a wafer fabrication line and an assembly line. The wafer fabrication line comprises a wafer completion process 1 for incorporating predetermined circuit functions into a wafer and a probe inspection process 2 for inspecting the operation of LSI chips in the wafer one by one, followed by the assembly line. The wafer completion process 1 mainly comprises a thermal oxidation process 1a typified by a thermal oxidation of silicon (Si), an impurity doping process 1b typified by ion implantation, a thin film formation process 1c typified by sputtering deposition of aluminum (A1) which utilizes a high-frequency plasma, a lithography process 1d which performs exposure for patterning and etching using oxygen plasma, and a cleaning process 1e.
In the assembly line, first in a dicing process, the LSI chips in the wafer are separated one by one, and the LSI chips which were judged to be non-defective in the probe inspection process are packaged in a packaging process 4. In the packaging process 4, the LSI chips are each sealed with resin together with lead pins, or hermetically sealed in a ceramic container, to complete a semiconductor device, or completed as TAB (tape automated bonding) in which electrodes of the LSI chip are connected to lead terminals formed on tape.
The LSI chips now in the form of finished products are aged in an aging process 5. The "aging" means an accelerated aging test in which a predetermined voltage is applied to each semiconductor device, allowing the semiconductor device to operate at a predetermined atmosphere temperature, for a predetermined time, for example a test in which each semiconductor device is operated at 125.degree. C. for 4 to 96 hours. The purpose of aging is for stabilizing the circuit operation of each semiconductor device and distinguishing defective semiconductor devices which are short in service life in the sense of reliability. According to an aging method commonly adopted, each LSI chip is placed into a socket on an aging board provided with required wiring and parts, and electric operations are performed in a constant high temperature vessel. In this aging process, a certain ratio of LSI chips which were even judged to be non-defective in the probe inspection process 2 are judged to be defective by being subjected to temperature stress and electrical stress for a predetermined time. It is presumed that such LSI chips came to have some cause of failure in the wafer fabrication line. Nevertheless, they were not judged to be defective in the probe inspection process, and there appeared failure mode in the aging process. The products found to be defective in the aging process 5 are removed in the next selection process 6, and only non-defective or conforming products are shipped. Thus, aging under appropriate conditions permits the shipment of only products having a sufficient useful life in actual use. In other words, the aging process is an indispensable process in the manufacture of semiconductor devices.
However, the following problems have been encountered in the aging process. Firstly, since the aging process is carried out after the packaging process 4, even defective chips short in life and low in reliability are assembled and thus eventually a wasteful work has been conducted. Secondly, although there is an increasing demand for packaging a semiconductor device in the state of a chip for attaining a high-density packaging, aging in the state of a chip is not performed in the foregoing semiconductor device manufacturing process and so the reliability of the semiconductor device obtained has been uncertain. Particularly, in the case of a product or a unit having plural chips as module, the probability of failure in aging of the product or the unit is high.
In view of the above circumstances, studies have recently been made about wafer aging in which aging is performed in the state of a wafer. However, wafer aging involves the following problems. It is difficult to make stable contact with electrodes on many and fine chips, and for making contact with such electrodes over a wide area of a wafer it is required to consider the flatness and thermal expansion of the wafer. Notwithstanding these problems, a wafer aging method has been proposed in which aging of wafer is performed after the wafer completion process 1 and before the probe inspection process 2. For example, in Japanese Patent Laid Open No. 167343/85, power application pads are formed on a wafer of the same material as that of a test wafer, then this wafer as a screening wafer is pushed against the test wafer, and aging is performed for all the chips on the wafer at a time. In Japanese Patent Laid Open No. 143436/87, electrodes for power supply with current limiting chip resistors connected thereto are provided on a substrate as electrifying jigs for effecting wafer aging. The current limiting chips are for preventing an excessively large current from flowing into shortage failure chips during aging. It has also been proposed to form slits in a substrate and make alignment by registration between the slits and alignment marks or scribing lines on a test wafer. According to a proposal made in Japanese Patent Laid Open No. 293629/87, a lid having a large number of needles capable of expanding and contracting vertically is pushed against a test wafer to obtain a stable contact state between chip electrodes and the needles. Further, in the above three conventional methods it is proposed to sandwich the aging substrate and the test wafer in between two plates, or sandwich the test wafer in between the aging substrate and one plate, to apply pressure, and perform aging in a fixed state.
If a defective product is detected by the wafer aging, it follows that a cause of this failure lies in the wafer fabrication line up to the completion of wafer. Therefore, by locating a failure process by analysis on the basis of such detected failure information, feeding the result of the analysis back to the wafer fabrication line quickly and repairing the failure process, it is possible to prevent further formation of such defective product.
In the above prior art methods, however, no consideration has been given to this point. In other words, no consideration has been made about the feedback to the wafer fabrication line of failure information on the reliability of chips for use in the improvement of the wafer fabrication line.
Moreover, according to the above conventional wafer aging methods, it has been difficult to effect aging for the chips on the whole area of a wafer correctly and efficiently under same and stable conditions. More particularly, the aging method disclosed in Japanese Patent Laid Open No. 143436/87 involves the problem that the aging equipment used is too large because it is required to use a large number of current limiting chip resistors. Next, the aging method disclosed in Japanese Patent Laid Open No. 293629/87 involves the problem that it is difficult to apply this method to the case where the chip electrode pitch on the wafer is narrow, say, 100 .mu.m or smaller. Further, the aging method disclosed in Japanese Patent Laid Open No. 143436/87 involves the problem that since the electrodes for power supply and the slits are formed separately, it is impossible to attain a high relative positional accuracy of the two and hence it is difficult to make accurate alignment of the power supply electrodes with respect to the electrodes on the whole area of the wafer. As to the operation of each chip during aging, the line voltage is apt to vary due to periodical changes of the supply current or due to the entry of electrical noises from the exterior, thus making it impossible to perform a stable operation, sometimes resulting in destruction of the chip. But means for preventing these inconveniences is not described at all in the above prior art publications, nor is given therein any consideration about aging a large number of wafers at a time and about pushing the power supply electrodes against the whole area of a wafer at a uniform pressure.
According to the foregoing conventional techniques, therefore, it has been impossible to effect the wafer aging correctly and efficiently, collect highly reliable failure information and feed back such failure information quickly to the wafer fabrication line.